1. Field of the Invention
The present invention relates to semiconductor memory devices. More particularly, the present invention relates to a method and circuit for cascading programmable impedance matching in a multi-chip memory system.
2. Background Information
A conventional Double Data Rate (DDR) static random access memory (SRAM) is a type of synchronous SRAM computer memory that can transfer up to two words of data in each access. A conventional Quad Data Rate (QDR) SRAM can transfer up to four words of data in each access. Conventional DDR and QDR SRAMs transfer data on both rising and falling edges of the clock signal, which doubles the maximum data transfer rate. These memory chips provide high performance architectures targeted at the next generation of, for example, switches and routers. Compared to existing memory solutions, QDR SRAMs are expected to greatly increase system memory bandwidth as well as serve as the main memory for lookup tables, linked lists, and controller buffer memory applications.
FIG. 1 illustrates a conventional system 100 for implementing impedance matching in memory devices. The conventional system 100 comprises a first QDR chip 102 coupled to second, third, and fourth QDR chips 104, 106, and 108, respectively, via a plurality of pull up program lines (e.g., PU_prog <0:n>). The first QDR chip 102 is configured to operate as a master chip which is coupled to a plurality of QDR chips 104, 106, and 108 that are configured to operate as slave chips. The impedance pin ZQ i2 of the first QDR chip 102 is coupled to a precision resistor Rq 110. No other QDR chips in the conventional system 100 are coupled to the precision resistor Rq 110. A pull up impedance calibration for the output driver is performed on the master QDR chip 102, and the impedance program lines are sent to the slave QDR chips 104, 106, and 108. Since, the ZQ pin i2 of the master QDR chip 102 is coupled to the precision resistor Rq 110, the impedance matching is performed by the master QDR chip 102 only, and the pull-up programming of the impedance is performed and transmitted to the plurality of slave QDR chips 104, 106, and 108 via the plurality of pull up program lines. A pull down programming of the impedance for the output driver is performed locally within every QDR chip. A disadvantage of the conventional system 100 is that there is an overhead of extra pins on each chip and multiple program lines on the board. Another disadvantage of the system 100 is that driver impedance mismatch between dies due to process, voltage, and temperature (PVT) variation is not compensated.
FIG. 2 illustrates a second conventional circuit 200 for implementing impedance matching in memory devices. The second conventional circuit 200 comprises a first QDR chip 202 coupled to second, third, and fourth QDR chips 204, 206, and 208, respectively, serially via signal lines, such as, for example, a clock signal zqclk 13, a load signal zqload i4 and a serial data signal zqdata i5. The first QDR chip 202 is configured to operate as the master chip and other QDR chips (204, 206, and 208) are configured to operate as slave chips. The pull up driver impedance calibration is performed on the master and is transmitted serially via the signal lines to the plurality of QDR chips 204, 206, and 208. The ZQ pin i2 of the master QDR chip 202 is coupled to the precision resistor Rq 210, and the impedance matching is performed by the first QDR chip 202 only. A pull up and pull down driver impedance calibration is also performed by the first QDR chip 202 only. A disadvantage of the circuit 200 is that there is an overhead of extra pins and multiple lines on the circuit board. Another disadvantage of system 200 is that driver impedance mismatch between dies due to PVT variation is not compensated.